The present invention relates generally to semiconductor devices, and, more particularly, to CMOS devices having transistors with mutually different punch-through voltage characteristics less susceptible to punch-through, and a method for manufacturing the same.
A CMOS device is generally- produced by forming PMOS and NMOS transistors in a semiconductor substrate, and electrically connecting them. Conventionally, after forming an N-well and P-well in the substrate, transistors having opposite conductivities are formed simultaneously in the wells and in the substrate between the wells, to thereby complete the CMOS. device.
FIG. 1 depicts a CMOS device manufactured by a conventional method, the CMOS device including a P-type semiconductor substrate 10, an N-well 18, a P-well 22, a field oxide layer 26, a gate oxide layer 28, and gate electrodes 30. The CMOS device depicted in FIG. 1 is formed by the steps of selectively doping opposite conductivity-type impurities in spaced-apart surface regions of the semiconductor substrate 10, to thereby form the N-well 18 and the P-well 22, respectively, forming the field oxide layer 26 in the conventional manner, forming the gate oxide layer 26 on the surface of the resultant structure, and forming the gate electrodes 30 on the gate oxide layer 28.
As semiconductor devices become more highly integrated, the unit size of the constituent devices thereof decreases, thus commensurately degrading the electrical characteristics of each constituent device. For example, in the case of a transistor, if the gap (channel) between the source and drain thereof is reduced, the incidence of punch-through due to contact between source and drain depletion regions thereof increases.
The lower the impurity concentration of the substrate, the more frequently punch-through occurs. The incidence of punch-through is particularly high in very small scale transistors, because a lower impurity concentration in the vicinity of the source and drain depletion regions and the substrate translates into larger source/drain depletion regions.
Significant research into a method for increasing the punch-through voltage of a transistor by increasing the impurity concentration in the vicinity of the source and drain depletion regions thereof has been actively carried out. In this connection, U.S. Pat. No. 4,354,307, entitled "Method for mass producing miniature field effect transistors in high density LSI/VLSI chips", issued to Vinson et al., discloses a method for increasing the punch-through voltage rating of a transistor by selectively increasing the impurity concentration of the substrate. However, since the bulk-concentrations of the wells and the substrate which crucially influence electrical characteristics of transistors respectively formed in the wells and the substrate are not selectively adjusted for each transistor, it is difficult to achieve the different electrical characteristics required for each transistor.
For example, if the transistor formed in the substrate requires a specific punch-through voltage and the transistor formed in the well requires a back-bias at a given operating voltage, the transistor formed in the substrate should have a high punch-through voltage, which is generally attained by increasing the bulk concentration of the depletion region thereof. Further, as suggested by the following equation (1), the transistor formed in the well should have a low gamma (.gamma.) value, which represents the variation of threshold voltage due to back-biasing &gt; EQU .gamma.=(2.epsilon..sub.s .epsilon..sub.0 qN.sub.a).sup.1/2 /C.sub.ox,(1)
where C.sub.ox is the capacitance of the gate oxide layer 28, .epsilon..sub.s is the dielectric constant of the semiconductor substrate 10, .epsilon..sub.0 is the dielectric constant of a vacuum, q is the charge quantity, and N.sub.a is the number of impurities. As can be understood from the above equation (1), in order to lower the .gamma. value, the value of qN.sub.a (i.e., bulk concentration) must be lowered. That is, when the transistor formed in the substrate requires a particular punch-through voltage and the transistor formed in the well requires reduced back biasing at a given operating voltage, the bulk concentration in the well should be different from that in the substrate.
However, using the conventional technique in which the respective bulk concentrations are not independently adjusted, it is not possible to manufacture transistors having mutually desirable characteristics at the same time. Rather, in order to achieve the required independent adjustment of the bulk concentrations, separate mask processing steps must be performed, which increases the cost and complexity, and reduces the efficiency and reliability of the manufacturing process.
Based on the above, it can be appreciated that there presently exists a need in the art for a CMOS device, and a method for manufacturing the same, which overcomes the above-described drawbacks and shortcomings of the presently available technology.